Cross correlator

ABSTRACT

Apparatus for cross-correlating a pair of electrical signals in which each signal is converted into a binary signal and fed to a feedback shift register. One of the registers has a delay in its feedback path. When the registers are full, the shift registers are continuously recycled and their outputs continuously compared by an exclusive - NOR gate. A counter coupled to the exclusive NOR gate counts the number of coincidences in a single cycle of the contents of the shift registers. This count is compared with the highest count attained in a previous cycle, the new count being held in a count store if higher than the previous highest count. The time between the start of the comparison and the time at which the highest count is obtained is stored in a separate time store. After each cycle the delay between the signals increases by one clock pulse. The time store then gives the delay for maximum correlation. In a further embodiment the invention operates with signals having three or more discrete levels in place of binary signals.

United States Patent [1 1 [111 3,777,133 Beck et al. Dec. 4, 1973 1CROSS CORRELATOR 3,463,911 8/1969 Dupraz er al. 235/181 [76] Inventors:Maurice Sidney Beck, 10 l-lazelhurst Filed: Jan. 24, 1972 Appl. No.:220,017

[30] Foreign Application Priority Data Jan. 26, 1971 Great Britain3,193/71 [52] US. Cl 235/181, 235/l51.34, 324/77 H, 343/100 CL [51] Int.Cl. G06g 7/19, G06f /34 [58] Field of Search 235/181, 151.34; 343/100CL, 112 R, 112 D; 324/77 G, 77 H [5 6] References Cited UNITED STATESPATENTS 3,036,775 5/1962 McDermid et al 235/181 X 3,532,867 10/1970Ricketts et a1 235/181 3,376,411 4/1968 Montani et a]. 235/181 X3,249,911 5/1966 Gustafsson 235/181 X 3,167,738 l/1965 Westerfield235/181 3,185,958 5/1965 Masterson et al. 235/181 X Y STORAGE F I fummzzn Primary ExaniinerFelix D. Gruber Attorney-Irvin S. Thompson eta1.

[5 7] ABSTRACT Apparatus for cross-correlating a pair of electricalsignals in which each signal is converted into a binary signal and fedto a feedback shift register. One of the registers has a delay in itsfeedback path. When the registers are full, the shift registers arecontinuously recycled and their outputs continuously compared by anexclusive NOR gate A counter coupled to the exclusive NOR gate countsthe number of coincidences in a single cycle of the contents of theshift registers. This count is compared with the highest count attainedin a previous cycle, the new count being held in a count store if higherthan the previous highest count. The time between the start of thecomparison and the time at which the highest count is obtained is storedin a separate time store. After each cycle the delay between the signalsincreases by one clock pulse. The time store then gives the delay formaximum correlation. In a further embodiment the invention operates withsignals having three or more discrete levels in place of binary signals.

6 Claims, 3 Drawing Figures um'r I 10 1 32 22 2 8 f W DIG/Um, SEQUENCE(OINCIDENCE commoner COUNTER comcmruce COUNT 510mm: STORE umr 1 T SLAVEEXECUTIVE TIMER ,CONTROLLER SYSTEM SCALER 1 VARIABLES I M /r 52 VISUAL56 DISPLAY PATENTEU 41973 SHEET 3 OF 3 1 0 0 0 1 1}4 N 1 1 0 1 C01CIDENCES (OINCIDENCES comcwmces 5 comcmmtzs CROSS CORRELATOR FIELD .ANDSUMMARY OF THE INVENTION This invention relates to apparatus for crosscorrelating electrical signals.

It is known to measure fluid flow velocity by cross correlating signalsrepresentative of the flow and obtained from positions spaced apart inthe direction of flow. A particular application of a preferredembodiment of the present invention described below is to crosscorrelate the electrical outputs of transducers arranged to detect suchsignals to provide a measure of the fluid flow velocity by determiningthe time delay between the two signals for maximum correlation. The meanfluid flow velocity is equal to the spacing between the two positionsdivided by such time delay. It will be appreciated, however, that theinvention is not limited to apparatus for use in this application, butincludes apparatus for cross correlating electrical signals from anysources. For instance, apparatus embodying the invention can also beused to cross correlate transmitted and return signals in wave energyposition finding systems such as radar or sonar to determine the timedelay therebetween.

According to the present invention, apparatus for cross correlating apair of electrical signals comprises shift registers associated withrespective signals and each adapted to store a series of signalelements, the signal elements in each series representing the magnitudeof the associated signal at succeeding instants in time, respectively,comparator means for comparing the signal element at the output stage ofone shift register with the signal element at the output stage of theother shift register and producing an output signal representingcorrespondence between the two elements, accumulator means foraccumulating output signals from the comparator means, control means forsupplying shift pulses to each shift register so that each element inthe register is advanced to the succeeding stage therein, feedback meansfor each shift register, each feedback means coupling the output stageof the associated register to the input stage thereof, one of thefeedback means including a delay, whereby the application of a number ofshift pulses corresonding to the number of stages in each registercauses a cycle of operation in which the elements stored in one shiftregister are returned to their original stages in the register and theelements in the other shift register are displaced by at least one stagerelative to their original stages, the control means supplying shiftpulses to cause a series of succeeding cycles of operation resulting ina progressively increasing displacement of the elements in one registerrelative to the elements in the other register, and the accumulatormeans providing, for each cycle of operation, a signal representative ofthe number of output signals from the comparator means, and hence thedegree of cross-correlation between the two electrical signals for atime delay corresponding to that cycle.

Clearly, the time delay between the pair of signals associated with thecycle producing the maximum total signal is the time delay between thesignals producing maximum cross correlation. In order that the maximumtotal signal may be determined automatically, the apparatus ispreferablyprovided with a first store connected to the accumulation means forstoring said total signal, a comparator connected to the first store andthe accumulation means for indicating when the total signal of theaccumulation means is greater than the total signal preserved in thefirst store, first means responsive to such indication being present atthe end of a cycle to cause the total signal of the accumulation meansto be entered into the first store in place of the total signalpreserved therein, and second means responsive to such indication beingpresent at the end of a cycle to record the time delay between said pairof signals for such cycle. Preferably said second means comprises acounter connected to count the number of cycles and a second store, andis responsive to said indication to enter the cycle number in thecounter into the second store. The cycle number is proportional to thetime delay between the pair of signals. It will be seen that once therequired number of cycles have taken place, the maximum total signaloccurring among all the cycles will be preserved in the first store andthe number of the associated cycle will be preserved in the secondstore. This cycle number is thus indicative of the time delay betweenthe two signals producing maximum correlation.

The apparatus may also include means for displaying the maximum totalsignal and/or the associated time delay, or further information computedtherefrom, e. g. fluid flow velocity in the above-mentioned preferredapplication. Further, the apparatus may have means for recording and/ordisplaying the total signal in the accumulation means at the end of eachcycle so as to record and/or display the cross correlation function ofthe pair of signals.

In a preferred embodiment of the invention the apparatus compares theamplitude values of successive elements of the pair of signals, whichare in binary form, and the multiplier means is then desirably acoincidence detector, i.e. a form of binary signal multiplier. Thisapparatus may include means for digitizing analogue input signals, suchmeans not being necessary if the signals are supplied to the apparatusin digital form. The digitizing means may in part comprise, for eachsignal, a respective polarity detector which produces a binary digitaloutput signal, the level of which is determined by the polarity of theanalogue input singal. The binary signals so-formed are digitized bybeing clocked into shift registers comprising said storage means. It iscontemplated, however, that binary signals produced by other techniques,or digital signals having more than two levels, may be used instead.

BRIEF DESCRIPTION OF THE DRAWINGS The invention maybe more readilyunderstood from the following description of two preferred embodimentsthereof, given by way of example only, having reference to theaccompanying drawings, in which:

FIG. 1 is a schematic view of a cross correlator in block diagram form;

F IG. 2 is a circuit diagram of a cross correlator which is similar tothat shown in block diagram form in FIG. 1; and

FIG. 3 shows a number of waveforms present during operation at differentpoints in the circuit of FIG. 2.

DESCRIPTION OF THE PREF ERRED EMBODIMENTS FIG. 1 shows in block diagramform an apparatus used to determine fluid flow velocity by crosscorrelating the electrical outputs of two transducers 10, 12 responsiveto fluid flow and spaced apart in the direction of flow. The apparatusis arranged to determine that value of time delay between the twosignals which produces maximum cross correlation and thereby todetermine the mean fluid flow velocity. The two electrical outputsignals from transducers and 12, x(t) and y(t) respectively, are appliedto respective digitizers 14 and 16. The outputs of the digitizers l4 and16 are connected to storage means comprising respective storage units 18and 20. The outputs of the storage units 18 and 20 are each connected toa respective input of an exelusive-OR coincidence detection gate 22arranged to produce an output when the signals at the inputs thereofcoincide. The outputs of the storage units 18 and 20 are also connectedby respective feedback circuits 24 and 26 to their respective inputs.The feedback circuit 26 includes a delay element and is controlled by asequence controller 32. The storage units 18, 20, and the sequencecontroller 32 are supplied with clock pulses over a conductor 34 from anexecutive controller 36. The clock pulses supplied by the executivecontroller 36 are derived from a master clock oscillator 38. Theexecutive controller 36 includes a frequency divider producing an outputapplied to a slave timer 40 which is arranged to supply low frequencyclock pulses to the digitizers 14 and 16.

Output signals from the coincidence detector 22 which indicatecoincidence of the storage units 18 and 20 are passed to and counted bya coincidence counter 28. The count stored in the counter 28 ismonitored by a comparator 42, which also monitors the count stored in acoincidence count store 30. The comparator 42 is arranged to transferthe total count in the counter 82 at the end of a cycle into the store30 when it exceeds the count preserved in the store 30. A time counter44 counts the number of cycles taking place. Whenever the comparator 42causes the coincidence count in the counter 28 to be transferred to thecoincidence count store 30 it also causes the time count in the counter44 to be transferred to the time store 46. The contents of thecoincidence counter 28 or the contents of the time store 46, or both arepassed to a modifier unit 48 when all the cycles have been completedwhere they are processed according to system scalar variables. Thesevariables may be representative of such factors as pipe diameter andflow rate range appropriate to a particular application. The comparator42 and the modifier 48 are also supplied with clock pulses from theexecutive controller 36.

The output of the modifier which constitutes the output of the apparatusmay be fed to one or more of a number of alternative read-out devices.These may comprise an analogue read-out unit 50, a digital display unit52, a unit 54 which divides the spacing between the two transducers bythe delay for maximum cross correlation determined by the apparatus toprovide a visual display of the fluid flow velocity at 56, an integrator58 which displays the total fluid throughout visually at 60, and avisual display 62. The visual display unit 62 may comprise a storageoscilloscope which is supplied at the end of each cycle by the modifier48 through appropriate conventional means (not shown) with an analoguevoltage proportional to the coincidence count of that cycle. Each suchvoltage will thus provide a bright point on the oscilloscope, and, onceall the cycles have been completed, the points will define a curveindicating the cross correlation function of the two signals x(t) andy(t).

The digital display device 52 may be of the type which displays a timedelay computed in one operation until a fresh time delay computed in thenext operation is ready.

The manner of operation of the apparatus is as follows. The digitalsignals from the outputs of the digitizers l4 and 16, which aregenerated at a frequency determined by the low frequency clock pulsesfrom the slave timer 40, are fed serailly into the storage units 18 and20. The frequency of the clock pulses supplied from the slave timer 40for this purpose is chosen in accordance with the transducer timeconstants. The capacities of the storage units 18 and 20 may be variedto suit particular applications and in this preferred embodiment theyare each one thousand bits. Once the storage units have been filled withthe digitized signal elements, the executive controller 36 inhibits thedigitizing operations, which take place at the relatively low clockfrequency, and starts'the process of determining the delay for maximumcorrelation, which takes place at the relatively high clock frequency,i.e. of the order of computing speeds. In this process successiveelements of the digitized signals stored in the storage units 18 and 20are sequentially applied together to the coincidence detector 22. Theyare also successively fed back via the feedback circuits 24 and 26 totheir respective inputs whereby when each element has been so fed backthe elements stored in the storage units are preserved in the same formas they were before the process commenced. However, the delay element inthe feedback circuit 26 delays the feedback to the storage unit 20 sothat at the end of the cycle whereas the elements in the storage unit 18are in the same positions as they were at the start of the cycle, thosein the unit 20 are displaced by a single element spacing.

The number of output signals from the coincidence detector 22 indicativeof a coincidence occurring between the elements stored in the units 18and 20 during one cycle is accumulated in the coincidence/counter 28.This count value is then compared with the count value preserved in thestore 30 and, if. it exceeds said stored value, it is entered into thestore 30 in place of said stored value. The counter 28 is then cleared.If the coincidence count is transferred into the store 30, the timecount (i.e. the cycle number) in the time counter 44 is transferred intothe time store 46. The whole comparison and feedback cycle is thenrepeated, but due to the elements stored in the storage unit 20 beingdisplaced by one element spacing, the elements of one stored signal arecompared with later elements of the other stored signal as compared tothe previous cycle. The number of coincidences recorded in the counter28 is again compared by the comparator 42 with the count accumulated inthe store 30 and the two stores 30 and 46 are again updated if thenumber of coincidences occurring during the cycle is greater than thegreatest number occurring during any previous cycle as recorded in thecoincidence count store 30.

The coincidence detection cycle is successively repeated until the twosets of signal elements have been compared for all possible relativedelays, i.e., when the elements are displaced by one element spacing percycle, until the number of cycles equals the number of elements of eachsignal stored. The count then stored in coincidence count store 30 isthe maximum cycle count occurring and during the associated cycle therewas thus maximum cross correlation between the two signals x(t) andy(t). The associated cycle number is preserved in the time store 46 andis fed into the modifier 40. The delay corresponding to such preservedcycle number may be calculated by the modifier 48 to assist in providingone of the displays at the unit 50, 52, 56, 60 or 62 as discussed above.I

It will be appreciated that the process for determining the maximumcorrelation may be speeded up, with a corresponding loss in accuracy, bydisplacing the elements in the storage unit 20 by two or more elementspacings, rather than by one, between each coincidence detection cycle.Alternatively, the process may be speeded up without loss in accuracy bymaking the cycle delay variable. For instance, if it is known that themaximum cross correlation between the two signals will occur when theyare relatively displaced by approximately 150 element spacings, thedelay can be set by known methods to 120 spacings for the first cycle,and thereafter to unity as above. Operating in this manner eliminates 120 low correlation cycles and thus speeds up the whole process. Thedelay could then be increased again at say 200 spacings after thecorrelation peak has clearly occurred, to further speed up theoperation.

F 1G. 2 is a circuit diagram of a cross correlator which is similar tothat shown in block diagram form in FIG. 1. The two analogue electricalsignal outputs from the transducers (not shown) are applied torespective polarity detectors 100 and 102. These detectors producebinary signal outputs, the levels of which are determined by thepolarities of the inputs, which are amplified by respective amplifiers104 and 106 and passed to respective NAND gates 108 and l which areenabled by a common signal on a conductor 120. The outputs of the NANDgates 100, 1 10 are connected to storage units which comprise shiftregisters 122 and 124. The outputs of the shift registers are eachapplied to a respective input of a coincidence detection gate 126 andare fed back to their inputs in similar manner to FIG. 1 via feedbackloops 120 and 130. The feedback loops 128 and 130 are controlled byrespective NAND gates 132 and 134 which are enabled by a common input onthe conductor 136. The feedback loop' 130 also includes a unit delaydevice 138.

A bistable device 112 having complementary outputs P AND O supplies saidenabling signals on the conductor 120 or the conductor 136 when theapparatus is in the read-in or the cycling mode respectively.

In like manner to FIG..1, the output from, the coincidence detectiongate 126 is passed to a coincidence counter 140. The counter 140 isarranged, on receipt of an appropriate instruction, to transfer itscontents in parallel to a coincidence count store 142. The contents ofthe counter 140 and of the store 142 are connected to be compared by acomparator 144'which is arranged to produce an output signal on anoutput conductor 146 when the contents of the store are greater than thecontents of the counter. Such signal is applied as one input to afurther NAND gate 148.

The apparatus is provided with a master clock oscillator 150 whichsupplies an output directly to a NAND gate 152 to provide the highfrequency clock pulses and by means of a frequency divider 154 toanother NAND gate 156, to provide the low frequency clock pulses. Theother inputs to the NAND gates 152 and 156 are provided, respectively,by said enabling signals from the bistable device 112 on a conductor 158and on the conductor 120. The outputs of the gates 152 and 156 areconnected together so as to supply either low or high frequency clockpulses, according to whether the apparatus is in the read-in or thecycling mode, to the shift registers 122 and 124, the coincidencecounter 140 and to a 1001 :1 frequency divider 160. The output of thedivider is connected to one input of each of two further NAND gates 162and 174, the NAND gate 148, and to an input of a NOR gate 164. It isalso connected by way of gate 164 to the coincidence counter 140 and tothe coincidence count store 142. The other input to the NAND gate 162 isprovided by the conductor 158, and the output of the gate 162 isconnected to the input of a time counter 166 which counts the number ofelapsed cycles. The counter 166 is arranged to transfer its contents toa further store 168 when enabled by a signal from the output of the NANDgate 148. The contents of the store 168 may be passed via a modifier, ifrequired, to a display (not shown) when cycling has finished, asdescribed above with reference to FIG. 1.

When the counter 166 is full it applies a signal as one input to a NORgate 170. The other input of the gate 170 is obtained from the output ofsaid NAND gate 174. The output from the gate 170 is connected via aconductor 172 to a toggling input of the bistable device 1 12.

The manner in which the apparatus determines the value of the delaybetween the two signals x( t) and y(t) which produces maximum crosscorrelation is described below. It is assumed that initially thebistable device 112 is in the state in which output P is active.Consequently, gates 108, 110, 156 and 174 are enabled, and gates 132,134, 152 are 162 are disabled.

The signals from the transducers applied to the inputs of the polaritydetectors and 102, as shown in FIG. 3 at A produce binary signals asshown in FIG. 3 at B which signals are amplified by the amplifiers 104and 106 and passed via the NAND gates 108 and to the shift registers 122and 124. As gate 156 is enabled and gate 152 is disabled, low frequencyclock pulses as shown in FIG. 3 at C are supplied to the shift registers122 and 124, and the signals B are thus clocked into the shift registersand digitized as shown in FIG. 3 at D, the corresponding binary valuesbeing shown at E. Ten bits only of the signals D and E are shown in FIG.3 for convenience. It will be appreciated that in practice 1,000 bitsare fed into the shift registers 122 and 124 in this manner.

Meanwhile, as the shift registers are being filled, the low frequencyclock pulses are also being fed into the divider 160. When the registersare full, i.e. when 1,000 bits are fed into each, one bit later thedivider provides an output indicating this. This output is passed viagates 174 and to the conductor 172 thus toggling the bistable device 112and putting the apparatus into the cycling or compute mode. This outputalso clears the counter 140 via the inverter 164.

Once the bistable device 112 changes state, the gates 108, 110, 156 and174 are disabled, and the gates 132, 134, 152 and 162 are enabled.Consequently, high frequency clock pulses are sent out in place of lowfrequency pulses, the gates 108 and 110 stop reading-in of the signals,and the feedback loops 128 and 130 are closed. The repetitive feedbackand coincidence detection cycling then takes place, at a much fasterfrequency than the speed at which the bits were clocked into the shiftregisters. The operation proceeds much in the same manner as describedabove with reference to FIG. 1. Each bit or element stored in the shiftregisters 122 and 124 is sequentially passed to the coincidencedetection gate 126 and is fed back round the feedback loops 128 and 130to its respective input. Due to the provision of the unit delay element138, after each operation, the elements stored in the shift register 124are displaced by a further bit period, and thus in each cycle thecomparison between the two series of elements is staggered by onefurther element.

The comparison between the two sets of stored elements for threesuccessive cycles is illustrated by way of example for bits only in FIG.3 at F, G, H and I. At F, the two sets of bits shown at E are showntogether as they are compared. At G, H and I the bits obtained from thesignal y(t) are shown displaced by one, two and three bit spacingsrespectively with respect to the bits obtained from the signal x(t). Itcan readily be seen that the number of coincidences for the four cycles,in order, is 4, 6, 7 and 5. Clearly then, the third cycle, shown at H,produces maximum correlation between the two signals.

The manner in which the apparatus of FIG. 2 operates when in the cycingmode will now be described in detail. Once cycling has started, highspeed clock pulses are continually fed to the shift registers 122 and124 and they are operative to continually recycle their contents via thefeedback loops 128 and 130, with an extra bit period's delay being addedinto the feedback loop 130 on each cycle. The coincidence counter 140counts the number of coincidences in each cycle as detected by the gate126.

The divider 160, which previously timed the read-in operation, now actsto time the cycles. Thus, once cycling has started, the divider 160produces an output after 1001 high frequency clock pulses to indicatethe end of the first cycle. This output enables the NAND gate 148 sothat the output of the comparator 144, which is continually comparingthe contents of the counter 140 and store 142, is connected to thecoincidence count store 142 and the time store 168. If the comparatoroutput signal as transmitted by the gate 148 indicates that the countpreserved in the store 142 is less than the count in the counter 140,the contents of the two counters 140 and 166 are passed to theirrespective associated stores 1412 and 1611. In this way, the two storescontinually record the coincidence count and the cycle number of thecycle which has had the greatest number of coincidences.

As well as enabling the gate 1418, the output from the divider clearsthe counter 140 via the NOR gate 164, and is passed via the gate 162 tothe time counter 166. This counter thus counts the number of cycleswhich is proportional to the time delay between the two signals x(t) andy(t).

When 1,000 cycles have taken place, i.e. when the full digitalcross-correlation function has been computed, the time counter providesan output signal on a conductor 176 which is connected to one input ofthe NOR gate 170. The output of this gate is then operative to togglethe bistable device 112 so that the apparatus is returned to the lowspeed read-in mode and the whole process of determining the time delayfor maximum cross correlation is then repeated for a new pair of samplesof the signals x(t), y(t).

The dual speed operating feature of the apparatus described enables therelatively low frequency digitizing operation to be compatible with thefast computing speeds necessary to provide a quick computation of thedelay for maximum correlation.

Various modifications of the apparatus described with reference to FIG.2 are contemplated. For instance, the operation of the apparatus may bespeeded up by continually updating the stored elements of signalinformation instead of renewing the contents of each storage unit afterthe delay for maximum correlation has been computed.

If required, the embodiment of FIG. 2 may be employed with a multiplexerso that it may process signals from several different sets oftransducers on a time division multiplex basis.

The cross correlation operation of the apparatus of FIG. 2 may bespeeded up, with or without consequent loss in accuracy, by the samemethods, mentioned hereinabove, as can be used for the apparatus of FIG.1.

The apparatus described provides for fast, on-line computation of thecross correlation between two electrical signals and can be simply andeconomically fabricated using standard logic units, obviating the needfor an expensive digital computer.

As was mentioned before, the present invention may operate with signalshaving three or more discrete levels rather than, as here, with binarysignals. It might, for example, be necessary to use more than two levelsto accommodate peculiarities of the input signal waveforms. In apparatusdesigned to operate on this basis, the shift registers could be replacedby groups of registers and the coincidence detector replaced by amultilevel multiplier circuit which multiplies together successivegroups of signal elements from each of the groups of registers toproduce a product signal. All the product signals produced in each cycleare added, e.g. by an analog addition circuit, or if the multiplierproduces a digital output, by a counter, to produce the total signal forthe cycle; and the apparatus determines the cycle in which the greatesttotal signal is produced in like manner to that described in the abovedescriptions of specific forms of cross correlation apparatus.

We claim: r

1. Apparatus for cross-correlating a pair of electrical signals,comprising shift registers associated with respective signals and eachadapted to store a series of signal elements, the signal elements ineach series representing the magnitude of the associated signal atsucceeding instants in time, respectively, comparator means forcomparing the signal element at the output stage of one shift registerwith the signal element at the output stage of the other shift registerand producing an output signal representing correspondence between thetwo elements, accumulator means for accumulating output signals from thecomparator means, control means for supplying shift pulses to each shiftregister so that each element in the register is advanced to thesucceeding stage therein, feedback means for each shift register, eachfeedback means coupling the output stage of the associated register tothe input stage thereof, one of the feedback means including a delay,whereby the application of a number of shift pulses corresponding to thenumber of stages in each register causes a cycle of operation in whichthe elements stored in one shift register are returned to their originalstages in the register and the elements in the other shift register aredisplaced by at least one stage relative to their original stages, thecontrol means supplying shift pulses to cause a series of succeedingcycles of operation resulting in a progressively increasing displacementof the elements in one register relative to the elements in the otherregister, and the accumulator means providing, for each cycle ofoperation, a signal representative of the number of output signals fromthe comparator means, and hence the degree of crosscorrelation betweenthe two electrical signals for a time delay corresponding to that cycle.

2. Apparatus as defined in claim 1 wherein the control means are adaptedto supply shift pulses at a relatively high frequency for the purposeset forth, or to supply shift pulses at a relatively low frequency forclocking said pair of signals into said shift registers prior to thecyclical application of the elements stored therein to said comparatormeans, and the control means includes means responsive to apredetermined number of elements having been fed into said shiftregisters to supply shift pulses at said relatively high frequency andmeans responsive to a predetermined number of cycles having taken placeto supply pulses at said relatively low frequency.

3. Apparatus as defined in claim 1, further including a first storeconnected to said accumulation means for storing said signal; a secondcomparator connected to said first store and said accumulation means forindicating when the signal of the accumulation means is greater than thesignal preserved in the first store; the second comparator includingmeans responsive to such indication at the end of a cycle to cause thesignal of said accumulation means to be entered into said first store inplace of the total signal preserved therein; and means responsive tosuch indication being present at the end of a cycle to record the timedelay between said pair of signals for such cycle.

4. Apparatus as defined in claim 3 wherein the lastnamed means comprisesa counter connected to count the number of cycles and a second store,and is responsive to said indication to enter the cycle number in saidcounter into said second store.

5. Apparatus as defined in claim 1, further comprising a respectivepolarity detector for each of said pair of signals for converting thesignals from an analog form into a binary form for supplying to saidshift registers.

6. Apparatus as defined in claim 1, further comprising means forconverting said pair of signals from an analog form into a form havingat least two discrete levels.

1. Apparatus for cross-correlating a pair of electrical signals, comprising shift registers associated with respective signals and each adapted to store a series of signal elements, the signal elements in each series representing the magnitude of the associated signal at succeeding instants in time, respectively, comparator means for comparing the signal element at the output stage of one shift register with the signal element at the output stage of the other shift register and producing an output signal representing correspondence between the two elements, accumulator means for accumulating output signals from the comparator means, control means for supplying shift pulses to each shift register so that each element in the register is advanced to the succeeding stage therein, feedback means for each shift register, each feedback means coupling the output stage of the associated register to the input stage thereof, one of the feedback means including a delay, whereby the application of a number of shift pulses corresponding to the number of stages in each register causes a cycle of operation in which the elements stored in one shift register are returned to their original stages in the register and the elements in the other shift register are displaced by at least one stage relative to their original stages, the control means supplying shift pulses to cause a series of succeeding cycles of operation resulting in a progressively increasing displacement of the elements in one register relative to the elements in the other register, and the accumulator means providing, for each cycle of operation, a signal representative of the number of output signals from the comparator means, and hence the degree of cross-correlation between the two electrical signals for a time delay corresponding to that cycle.
 2. Apparatus as defined in claim 1 wherein the control means are adapted to supply shift pulses at a relatively high frequency for the purpose set forth, or to supply shift pulses at a relatively low frequency for clocking said pair of signals into said shift registers prior to the cyclical application of the elements stored therein to said comparator means, and the control means includes means responsive to a predetermined number of elements having been fed into said shift registers to supply shift pulses at said relatively high frequency and means responsive to a predetermined number of cycles having taken place to supply pulses at said relatively low frequency.
 3. Apparatus as defined in claim 1, further including a first store connected to said accumulation means for storing said signal; a second comparator connected to said first store and said accumulation means for indicating when the signal of the accumulation means is greater than the signal preserved in the first store; the second comparator including means responsive to such indication at the end of a cycle to cause the signal of said accumulation means to be entered into said first store in place of the total signal preserved therein; and means responsive to such indication being present at the end of a cycle to record the time delay between said pair of signals for such cycle.
 4. Apparatus as defined in claim 3 wherein the last-named means comprises a counter connected to count the number of cycles and a second store, and is responsive to said indication to enter the cycle number in said counter into said second store.
 5. Apparatus as defined in claim 1, further comprisinG a respective polarity detector for each of said pair of signals for converting the signals from an analog form into a binary form for supplying to said shift registers.
 6. Apparatus as defined in claim 1, further comprising means for converting said pair of signals from an analog form into a form having at least two discrete levels. 